A high-performance framework for a network programmable packet processor using P4 and FPGA-Reference-Cited by-同舟云学术

A high-performance framework for a network programmable packet processor using P4 and FPGA

Published:2020-04 Issue: Volume:156 Page:102564
ISSN:1084-8045
Container-title:Journal of Network and Computer Applications
language:en
Short-container-title:Journal of Network and Computer Applications

Author:

Yazdinejad Abbas,Parizi Reza M.,Bohlooli Ali,Dehghantanha Ali,Choo Kim-Kwang Raymond

Funder

UTSA

ITESM

Publisher

Elsevier BV

Subject

Computer Networks and Communications,Computer Science Applications,Hardware and Architecture

Reference53 articles.

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4. Berde P, Gerola M, Hart J, Higuchi Y, Kobayashi M, Koide T, Lantz B, O'Connor B, Radoslavov P, Snow W, Parulkar G. ONOS: towards an open, distributed SDN OS. InProceedings of the Third Workshop on Hot Topics in Software Defined Networking 2014 Aug 22 (pp. 1-6). ACM.

5. Bringing programmability to the data plane: packet processing with a NoC-enhanced FPGA;Bitar,2015

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