Hardware accelerator for training with integer backpropagation and probabilistic weight update

Author:

Park Hyunbin,Kim Shiho

Funder

Ministry of Science, ICT and Future Planning

Publisher

Elsevier

Reference35 articles.

1. A survey of accelerator architectures for deep neural networks;Chen;Engineering,2020

2. Model compression and hardware acceleration for neural networks: a comprehensive survey;Deng;Proc. IEEE,2020

3. Wei, Bingzhen, Xu Sun, Xuancheng Ren, and Jingjing Xu. (2017) ”Minimal Effort Back Propagation for Convolutional Neural Networks.” arXiv preprint arXiv:1709.05804.

4. A 2.25 TOPS/W fully-integrated deep CNN learning processor with on-chip training;Lu,2019

5. An energy-efficient deep convolutional neural network training accelerator for in situ personalization on smart devices;Choi;IEEE J. Solid State Circuits,2020

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