Inter-line level schemes for handling hard errors in PCMs-Reference-Cited by-同舟云学术

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Inter-line level schemes for handling hard errors in PCMs

Published:2020 Issue: Volume: Page:49-78
ISSN:0065-2458
Container-title:Advances in Computers
language:
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Author:

Asadinia Marjan,Sarbazi-Azad Hamid

Publisher

Elsevier

Reference30 articles.

1. Dynamically replicated memory: building reliable systems from nanoscale resistive memories;Ipek,2010

2. FREE-p: protecting non-volatile memory against both hard and soft errors;Yoon,2011

3. The Harey Tortoise: managing heterogeneous write performance in SSDs;Grupp,2013

4. Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset;Martin;ACM CAN,2005

5. Simics: a full system simulation platform;Magnusson;Computer,2002

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Seeds of SEED: R-SAW: New Side Channels Exploiting Read Asymmetry in MLC Phase Change Memories;2021 International Symposium on Secure and Private Execution Environment Design (SEED);2021-09

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