Design and Analysis of 8 Bit Parallel Prefix Comparators Using Constant Delay Logic

Author:

George Amy Mariam,Chandran G. Jyothish

Publisher

Elsevier BV

Subject

General Earth and Planetary Sciences,General Environmental Science

Reference8 articles.

1. High-performance and power-efficient CMOS comparators;Huang;IEEE J. Solid-State Circuits,2003

2. Bitwise competition logic for compact digital comparator;Kim;in Proc. IEEE Asian Solid-State Circuits Conf,2007

3. A low-power high-performance single-cycle tree-based 64-bit binary comparator;Chuang;IEEE Trans. Circuits Syst. II, Exp. Briefs,2012

4. A 167-ps 2.34-mW Single-Cycle 64-Bit Binary Tree Comparator With Constant-Delay Logic in 65-nm CMOS;Chuang;IEEE Transactions On Circuits And Systems—I: Regular Papers,2014

5. Analysis of high-performance fast feedthrough logic families in CMOS;Navarro-Botello;IEEE Trans. Circuits Syst. II, Exp. Briefs,2007

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