Phosphorene source engineered stacked metal gate tunnel field effect transistor with enhanced scaling-Reference-Cited by-同舟云学术

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Phosphorene source engineered stacked metal gate tunnel field effect transistor with enhanced scaling

Published:2018-12 Issue: Volume:124 Page:52-61
ISSN:0749-6036
Container-title:Superlattices and Microstructures
language:en
Short-container-title:Superlattices and Microstructures

Author:

Kumar Mirgender,Seong Kwang-Su,Park Si-Hyun

Funder

Human Resources Program in the Transportation Specialized Lighting Core Technology Development

Ministry of Trade, Industry & Energy, Republic of Korea

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference41 articles.

1. FinFETs and Other Multi-gate Transistors by;Colinge,2008

2. The fundamental downscaling limit of field effect transistors;Mamaluy;Appl. Phys. Lett.,2015

3. Green transistor as a solution to the IC power crisis;Hu;Proc. 9th Int. Conf. Solid-State Int. Circuit Technol.,2008

4. Effect of single HALO doped channel;Syamal,2010

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. An Ultra-Low-Power Black Phosphorus (B-Ph)/Si Heterojunction Dopingless-Tunnel FET (HD-TFET) with Enhanced Electrical Characteristics;Superlattices and Microstructures;2021-01

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