Improving the performance of dual-k spacer underlap Double Gate TFET

Author:

Chauhan Abhinav,Saini Gaurav,Yerur Pavan Kumar

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference19 articles.

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2. Novel Tunneling Devices for Future CMOS Technologies;Bhuwalka,2005

3. Maintaining the benefits of CMOS scaling when scaling bogs down;Nowak;Journal of Research and Development,2002

4. Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec;Choi;IEEE Electron. Device Lett.,2007

5. Band-to-band tunneling in carbon nanotube field-effect transistors;Appenzeller;Phys. Rev. Lett.,2004

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2. A Review on Role of Epitaxial Engineering in Improving the Drive Current and Subthreshold Swing in Area Scaled Tunnel FETs;2023 International Conference on Computer, Electronics & Electrical Engineering & their Applications (IC2E3);2023-06-08

3. Investigation of electrical parameters and temperature analysis of a dual-metal DG PNPN TFET with extended source;Engineering Research Express;2023-05-22

4. Electrical noise in Ge-source double-gate PNPN tunnel field effect transistor;Indian Journal of Physics;2022-10-30

5. A Review of Tunnel Field-Effect Transistors for Improved ON-State Behaviour;Silicon;2022-07-23

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