Elliptical nanowire FET: Modeling the short-channel subthreshold current caused by interface-trapped-charge and its evaluation for subthreshold logic gate

Author:

Chiang Te-Kuang

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Condensed Matter Physics,General Materials Science

Reference16 articles.

1. High Performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling;Bangsaruintip,2009

2. Vertically stacked silicon nanowire transistors fabricated by inductive plasma etching and stress-limited oxidation;Ng;IEEE Electron. Device Lett.,2009

3. Modeling short-channel effect of elliptical Gate-All-Around MOSFET by effective radius;Zhang;EEE Electron Device Lett.,2011

4. Analysis and implementation of subthreshold adiabatic logic design for ultralow-power applications;Athreya,2018

5. implementation of subthreshold adiabatic logic for ultralow-power application;Chanda;IEEE Trans. Very Large Scale Integr. Syst.,2015

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