On chip network with increased performance for efficient wireless communication

Author:

Ponnan Suresh,Kumar Tikkireddi Aditya

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering,Industrial and Manufacturing Engineering,Mechanics of Materials,Electronic, Optical and Magnetic Materials

Reference37 articles.

1. On-chip interconnection networks of the TRIPS chip;Gratz;IEEE Micro,2007

2. An 80-tile 1.28TFLOPS network-on-chip in 65nm CMOS;Vangal,2007

3. Modeling, Analysis and Optimization of Network-On-Chip Communication Architectures;Ogras,2013

4. Centralized buffer router: a low latency, low power router for high radix NOCs;Hassan,2013

5. Path-congestion-aware adaptive routing with a contention prediction scheme for network-on-chip systems;Chang;IEEE Trans on Computer-Aided Design of Integrated Circuits and Systems,2014

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