A synchronous comparator architecture for the design of deadtimeless front-ends in high-rate pixellated detectors

Author:

Gaioni L.,Traversi G.

Funder

Instituto Nazionale di Fisica Nucleare

Publisher

Elsevier BV

Subject

Instrumentation,Nuclear and High Energy Physics

Reference8 articles.

1. Design techniques for high-speed, high-resolution comparators;Razavi;IEEE J. Solid-State Circuits,1992

2. M. Campbell, Electronics for pixel detectors, in: Proc. LEB2001 Workshop on Electronics for LHC Experiments, Stockholm, Sweden, 2001, C01-09-10.12.

3. A review of advances in pixel detectors for experiments with high rate and radiation;Garcia-Sciveres;Rep. Progr. Phys.,2018

4. A 65 nm CMOS analog processor with zero dead time for future pixel detectors;Gaioni;Nucl. Instrum. Methods,2017

5. In-Pixel Readout IC with Compact in-Pixel ADC for Pixel Detectors at HL LHC;Parpillon,2023

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