Towards third generation pixel readout chips

Author:

Garcia-Sciveres M.,Mekkaoui A.,Ganani D.

Publisher

Elsevier BV

Subject

Instrumentation,Nuclear and High Energy Physics

Reference10 articles.

1. The FE-I4 pixel readout integrated circuit

2. T. Hemperek, et al., Digital architecture of the new ATLAS pixel chip FE-I4, in: Nuclear Science Symposium Conference Record (NSS/MIC), IEEE, 2009, pp. 791–796.

3. ATLAS Collaboration, The ATLAS insertable B-layer pixel detector, PoS VERTEX2011 (2011), p. 018.

4. R. Ballabriga, et al., Journal of Instrumentation, http://dx.doi.org/10.1088/1748-0221/8/02/C02016, in press.

5. W. Wong, A Hybrid Pixel Detector ASIC with Energy Binning for Real-Time, Spectroscopic Dose Measurements, Ph.D. Thesis, Mid Sweden University, 2012, ISBN:978-91-87103-20-9.

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2. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC;Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment;2017-02

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4. New development on digital architecture for efficient pixel readout ASIC at extreme hit rate for HEP detectors at HL-LHC;2016 IEEE Nuclear Science Symposium, Medical Imaging Conference and Room-Temperature Semiconductor Detector Workshop (NSS/MIC/RTSD);2016-10

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