1. VLSI implementation of low power scan based testing;Ukey,2016
2. At-speed testing of delay faults for Motorola's MPC7400, a PowerPCTM microprocessor;Tendolkar,2000
3. At-speed structural test for high-performance ASICs;Iyengar,2006
4. Logic design for on-chip test clock generation - implementation details and impact on delay test quality;Beck,2005
5. Design for test features of the ARM clock control macro;Frederick,2007