Author:
Ben Abdelali Abdessalem,Chatti Ichraf,Hannachi Marwa,Mtibaa Abdellatif
Reference24 articles.
1. A pipelined fast 2D-DCT accelerator for FPGA-based SoCs;Turneo;Proc - IEEE Comput Soc Annu Symp VLSI Emerg VLSI Technol Archit,2007
2. FPGA implementation of a DA based 1D DCT processor;Road;Int J Rev Electron Commun Eng,2013
3. Design of low power 2-D DCT architecture using reconfigurable architecture;Venkata;IOSR J Electron Commun Eng,2012
4. Fast multiplierless approximations of the DCT with the lifting scheme;Liang;IEEE Trans Signal Process,2001
5. Development of integer cosine transforms by the principle of dyadic symmetry;Cham;IEE Proc I - Commun Speech Vis,1989
Cited by
3 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献