A design based on proven concepts of an SEU-immune CMOS configuration data cell for reprogrammable FPGAs
Author:
Publisher
Elsevier BV
Subject
General Engineering
Reference13 articles.
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1. Concurrent error detection for finite state machines implemented with embedded memory blocks of SRAM-based FPGAs;Microprocessors and Microsystems;2008-08
2. Designing CMOS data cells for space systems;Microelectronics Journal;2004-12
3. A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs;Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921)
4. Fault Tolerance in Programmable Circuits;Radiation Effects on Embedded Systems
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