Voltage stress induced interface states and hole trapping in germanium pMOSFETs with high-k gate dielectric and metal-gate electrode

Author:

Chiu Fu-ChienORCID,Chen Wei-Chia,Wu Jih-Huah,Chang-Liao Kuei-ShuORCID

Funder

Ministry of Science and Technology, Taiwan

Publisher

Elsevier BV

Subject

Mechanical Engineering,Mechanics of Materials,Condensed Matter Physics,General Materials Science

Reference23 articles.

1. The ultimate CMOS device and beyond;Kuhn,2012

2. A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors;Ghani,2003

3. Strained Si, SiGe, and Ge channels for high-mobility metal-oxide-semiconductor field-effect transistors;Lee;J. Appl. Phys.,2005

4. III-V/Ge channel MOS device technologies in nano CMOS era;Takagi;Jpn. J. Appl. Phys.,2015

5. High-κ gate dielectrics: current status and materials properties considerations;Wilk;J. Appl. Phys.,2001

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