1. Semiconductor Industry Association, The International Technology Roadmap for Semiconductors (ITRS 2015), (Available at http://www.itrs2.net).
2. Embedded SRAM circuit design technologies for a 45 nm and beyond;Yamauchi,2007
3. Fluctuation limits & scaling opportunities for CMOS SRAM cells;Bhavnagarwala,2005
4. Static noise margin variation for sub-threshold SRAM in 65-nm CMOS;Calhoun;IEEE J. Solid State Circ.,2006
5. SRAM cell static noise margin and VMIN sensitivity to transistor degradation;Krishnan,2006