ATM switch architectures with input-output-buffering: effect of input traffic correlation, contention resolution policies, buffer allocation strategies and delay in backpressure signal-Reference-Cited by-同舟云学术

ATM switch architectures with input-output-buffering: effect of input traffic correlation, contention resolution policies, buffer allocation strategies and delay in backpressure signal

Published:1994-05 Issue:9 Volume:26 Page:1187-1213
ISSN:0169-7552
Container-title:Computer Networks and ISDN Systems
language:en
Short-container-title:Computer Networks and ISDN Systems

Author:

Badran Hosein F.,Mouftah H.T.

Publisher

Elsevier BV

Subject

General Engineering

Reference25 articles.

1. A survey of modern high performance switching techniques;Ahmadi;IEEE J. Selected Areas Comm.,1989

2. A high performance switch fabric for integrated circuit and packet switching;Ahmadi,1988

3. H.F. Badran, Design and Performance analysis of nonblocking ATM switch architectures, Ph.D. Thesis, Dept. of Electrical Engineering, Queen's University, Canada, under preparation.

4. Fairness for broadband integrated switch architectures under backpressure mechanisms;Badran,1991

5. Head of line arbitration in ATM switches with input-output buffering and backpressure control;Badran,1991

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3. Networking Algorithms and Computational Intelligence;Computational Intelligence in Telecommunications Networks;2000-09-15

4. Performance analysis of fuzzy thresholding-based buffer management for a large-scale cell-switching network;IEEE Transactions on Fuzzy Systems;2000

5. A guaranteed-no-cells-dropped buffer management scheme with selective blocking for cell-switching networks;Computer Communications;1998-07