Specification and Verification of Hardware Systems using the Temporal Logic Language TRIO 11This work was partially supported by CNR-Progetto Finalizzato Sistemi Informatici e Calcolo Parallelo and by ENEL-CRA

Author:

Coen-Porisini Alberto,Morzenti Angelo,Sciuto Donatella

Publisher

Elsevier

Reference23 articles.

1. “VHDL Language reference manual, version 7.2” Intermetrics Rep. IR-MD-045–2, Aug. 1985.

2. “VHDL critique”;Nash;IEEE Design and Test of Comp.,1986

3. N.Suzuki, “Concurrent Prolog as an efficient VLSI design language”, IEEE Computer Mag., pp.33–40, Feb.85.

4. “Logic circuit synthesis using Prolog”;Uehara;New Generation Comput.,1983

5. “Temporal Logic of Programs”;Kröger,1987

Cited by 2 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Real-time systems: A survey of approaches to formal specification and verification;Lecture Notes in Computer Science;1993

2. Functional Test Case Generation for Real-Time Systems;Dependable Computing for Critical Applications 3;1993

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