1. Design, implementation, and test of a multi-model systolic neural-network accelerator;Cornu;Scientific Programming,1996
2. Design and Analysis of a Systolic Array for Neural Computation;Viredaz,1994
3. Programmable VLSI Systolic Processors for Neural Network and Matrix Computations;Lopez,1996
4. Quantization effects in digitally behaving circuit implementations of Kohonen networks;Thiran;IEEE Transactions on Neural Networks,1994