A butterfly processor-memory interconnection for a vector processing environment

Author:

Brooks Eugene D

Publisher

Elsevier BV

Subject

Artificial Intelligence,Computer Graphics and Computer-Aided Design,Computer Networks and Communications,Hardware and Architecture,Theoretical Computer Science,Software

Reference5 articles.

1. Effects of synchronization barriers on multiprocessor performance;Axelrod;Parallel Comput.,1986

2. Analysis and simulation of Banyan interconnection networks with 2 × 2, 4 × 4 and 8 × 8 switch elements;Cheemalavagu,1982

3. Analysis and simulation of buffered delta networks;Dias;IEEE Trans. Comput.,1981

4. Performance of processor-memory interconnections for multiprocessors;Patel;IEEE Trans. Comput.,1981

5. Reduced instruction set computers;Patterson;Comm. ACM.,1985

Cited by 6 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. Design and Analysis of a Scalable, Shared-memory System with Support for Burst Traffic;Scalable Shared Memory Multiprocessors;1992

2. A survey of commercial parallel processors;ACM SIGARCH Computer Architecture News;1988-09

3. The indirect k-ary n-cube for a vector processing environment;Parallel Computing;1988-03

4. The shared memory hypercube;Parallel Computing;1988-02

5. The butterfly barrier;International Journal of Parallel Programming;1986-08

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