The word-invalidate cache coherence protocol
Author:
Publisher
Elsevier BV
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference13 articles.
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3. Reducing coherence overhead and boosting performance of high-end SMP multiprocessors running a DSS workload;Journal of Parallel and Distributed Computing;2005-03
4. Simulation study of memory performance of SMP multiprocessors running a TPC-W workload;IEE Proceedings - Computers and Digital Techniques;2004
5. PSCR: a coherence protocol for eliminating passive sharing in shared-bus shared-memory multiprocessors;IEEE Transactions on Parallel and Distributed Systems;1999-07
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