62.5 ps LSB resolution multiphase clock Time to Digital Converter (TDC) implemented on FPGA
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Published:2021-02
Issue:
Volume:
Page:
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ISSN:1018-3639
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Container-title:Journal of King Saud University - Engineering Sciences
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language:en
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Short-container-title:Journal of King Saud University - Engineering Sciences
Author:
Mattada MahanteshORCID,
Guhilot Hansraj
Subject
General Engineering
Reference20 articles.
1. The GANDALF 128-channel time-to-digital converter;Büchele;Phys. Procedia,2012
2. Chen, P., Cheng, H.C., Widodo, A., Tsai, W.X., 2013. A PVT insensitive field programmable gate array time-to-digital converter. NoMe – TDC 2013 – 2013 IEEE Nord. Mediterr. Work. Time to Digit. Convert. Proc., pp. 18–21. https://doi.org/10.1109/NoMeTDC.2013.6658232
3. A time-to-digital converter based on a multiphase reference clock and a binary counter with a novel sampling error corrector;Choi;IEEE Trans. Circuits Syst. II,2012
4. Fries, M.D., Williams, J.J., 2003. High-precision TDC in an FPGA using a 192 MHz quadrature clock, 580–584. https://doi.org/10.1109/nssmic.2002.1239380
5. ADC and TDC implemented using FPGA;Jinyuan;IEEE Nucl. Sci. Symp. Conf. Rec.,2007
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