Author:
Vaithiyanathan D.,Nargis J.,Seshasayanan R.
Cited by
13 articles.
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1. A Modified Viterbi Decoder Architecture for Hardware Efficiency;2023 3rd International Conference on Emerging Frontiers in Electrical and Electronic Technologies (ICEFEET);2023-12-21
2. Locate: Low-Power Viterbi Decoder Exploration using Approximate Adders;Proceedings of the Great Lakes Symposium on VLSI 2023;2023-06-05
3. An Efficient Viterbi Algorithm for Communication System;International Journal of Next-Generation Computing;2022-10-31
4. Power and area optimized adaptive Viterbi decoder for high speed communication applications;International Journal of Information Technology;2022-08-22
5. An Efficient Viterbi Algorithm for Communication System;Research Journal of Engineering and Technology;2022-03-31