Techniques to increase the schedulable utilization of cache-based preemptive real-time systems

Author:

Busquets-Mataix José V.,Gil Daniel,Gil Pedro,Wellings Andy

Publisher

Elsevier BV

Subject

Hardware and Architecture,Software

Reference39 articles.

1. R. Arnold, F. Mueller, D. Whalley, M.G. Harmon, Bounding worst-case instruction cache performance, in: Proceedings of the 15th IEEE Real-Time Systems Symposium, 1994, pp. 172–181

2. N. Audsley, A. Burns, M. Richardson, A. Wellings, Hard real-time scheduling: The deadline monotonic approach, in: Proceedings of the Eighth IEEE Workshop on Real-Time Operating Systems and Software, 1991

3. N. Audsley, Resource Control for Hard Real-Time Systems: a Review, Technical report YCS159, Department of Computer Science, University of York, 1991

4. The STRESS hard real-time system simulator;Audsley;Software-Practice and Experience,1994

5. S. Basumallick, K.D. Nilsen, Cache issues in real-time systems, in: Proceedings of the ACM SIGPLAN Workshop on Language, Compiler, and Tool Support for Real-Time Systems, 1994

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