Dual damascene advanced interconnects: new copper seed layer enhancement process metrology using ion chromatography

Author:

Lee Shih-Wei,Shi Frank G,Lopatin Sergey D

Publisher

Elsevier BV

Subject

General Engineering

Reference14 articles.

1. Stress effects in thermal cycling of copper (magnesium) thin films;Toomey;Appl. Phys. Lett.,1995

2. Stress in copper seed layer employing in the copper interconnection;Hara;Electrochem. Solid-State Lett., Electrochem. Soc.,2001

3. T. Kinoshita, H. Koerner, M. Murakami, Y. Yasuda, N. Kobaysahi, Characterization of electrochemical deposition (ECD) Cu process comparison between PVD and CVD seed layer, Proceedings of Advanced Metallization Conference (AMC), 1999, pp. 129–134.

4. U. Cohen, Seed layers for interconnects and methods for fabricating such seed layers, US Patent 6,136,707, October 24, 2000 and other pending patent applications.

5. Semiconductor Fabtech;Chen,2000

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2. An Empirical Relation between the Plating Process and Accelerator Coverage in Cu Superfilling;Bulletin of the Korean Chemical Society;2012-05-20

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4. Cu Electrodeposition on Resistive Substrates in Alkaline Chemistry: Effect of Current Density and Wafer RPM;Journal of The Electrochemical Society;2011

5. A Study on Seed Damage in Plating Electrolyte and Its Repairing in Cu Damascene Metallization;Journal of The Electrochemical Society;2010

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