A 12-bit 100 MS/s pipelined ADC without using front-end SHA
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference12 articles.
1. A 12 bit 200 MS/s zero-crossing-based pipelined ADC with early sub-ADC decision and output residue background calibration;Soon-Kyun;IEEE J Solid-State Circuits,2014
2. A 12-bit 20 MS/s 56.3 mW pipelined ADC with interpolation-based nonlinear calibration;Jie;IEEE Trans Circuits Syst I: Regular Papers,2012
3. A high-linearity pipelined ADC with opamp split-sharing in a combined front-end of S/H and MDAC1;Zhenyu;IEEE Trans Circuits Syst I: Regular Papers,2013
4. A 12 bit 50 MS/s CMOS Nyquist A/D converter with a fully differential class-AB switched Op-Amp;Young-Ju;IEEE J State Circuits,2010
5. A 1.8V 36-mW 11-bit 80MS/s pipelined ADC using capacitor and opamp sharing;Sasidhar;IEEE Asian Solid-State Circuits Conf, 2007. ASSCC '07,2007
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1. A New Low-Power Non-uniform Sample and Hold Circuit for Biomedical Signal Processing Applications;Circuits, Systems, and Signal Processing;2024-06-09
2. A high accuracy current charge-pump based MDAC for pipelined ADCs;AEU - International Journal of Electronics and Communications;2019-03
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