Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application-Reference-Cited by-同舟云学术

Design and analysis of PVT tolerant hybrid current starved ring VCO with bulk driven keeper technique at 45 nm CMOS technology for the PLL application

Published:2024-01 Issue: Volume:173 Page:154987
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Sivasakthi M.,Radhika P.

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference42 articles.

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3. Modelling and Optimization of Phase Locked Loop under Constrained Channel Length and Width of MOSFETs;Nanda;SILICON,2022

4. Sivasakthi M, Radhika P. “Performance Comparison of MCML, PFSCL, and Dynamic CML Gates with Parametric Analysis in 45 nm CMOS Technology,” pp. 451–463, 2023, doi: 10.1007/978-981-19-7753-4_35.

5. Sivasakthi M, Radhika P. “A High-Speed MCML Logic Gate and Multiplexer Design in 45 nm CMOS Technology,” pp. 01–05, 2023, doi: 10.1109/icerect56837.2022.10059652.

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