A FPGA-based digital synchronous methodology for IEC 61850-9-2 process bus
Author:
Publisher
Elsevier BV
Subject
Electrical and Electronic Engineering
Reference29 articles.
1. Das N, Aung TT, Islam S. Process-to-bay level peer-to-peer network delay in IEC 61850 substation communication systems. In: Australasian universities power engineering conference, (AUPEC); 2013. p. 1–6.
2. Modelling and analysis of IEC 61850 for end-to-end delay characteristics with various packet sizes in modern power substation systems;Wong,2014
3. Kumar S, Das N, Islam S. Performance monitoring of a PMU in a microgrid environment based on IEC 61850-90-5. In: Proceedings of the 2016 australasian universities power engineering conference, (AUPEC). p. 1–5.
4. Das N, Ma W, Islam S. Analysis of end-To-end delay characteristics for various packets in IEC 61850 substation communications system. In: Australasian universities power engineering conference: challenges for future grids, (AUPEC); 2015. p. 1–5.
5. Kumar S, Das N, Islam S. Performance evaluation of a process bus architecture in a zone substation based on IEC 61850-9-2. In: Proceedings of the 2015 IEEE PES asia-pacific power and energy engineering conference, (APPEEC). p. 1–5.
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1. Design of Hardware Setup Based on IEC 61850 Communication Protocol for Detection & Blocking of Harmonics in Power Transformer;Energies;2021-12-09
2. A Novel NOR Gate-Based Dynamic Power Gating Technique in SRAM;Lecture Notes in Electrical Engineering;2020-09-20
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