A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information-Reference-Cited by-同舟云学术

A 1.8 V 3 GS/s 7-bit time-interleaved Quasi C-2C SAR ADC using voltage-comparator time-information

Published:2018-01 Issue: Volume:83 Page:138-149
ISSN:1434-8411
Container-title:AEU - International Journal of Electronics and Communications
language:en
Short-container-title:AEU - International Journal of Electronics and Communications

Author:

Nasiri Hamed,Nabavi Abdolreza^ORCID

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference15 articles.

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2. Choi M. Abidi AA, A 6 b 1.3 GSample/s A/D converter in 0.35/spl mu/m CMOS. Paper presented at the 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177) 2001;7–7 Feb. 2001.

3. Ying-Zu L. Soon-Jyh C. Yen-Ting L. Chun-Cheng L. Guang-Ying H, A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS. Paper presented at the 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers 2009;8–12 Feb. 2009.

4. Varonen M. Kaltiokallio M. Saari V. Viitala O. Karkkainen M. Lindfors S. Halonen KAI, A 60-GHz CMOS receiver with an on-chip ADC. Paper presented at the 2009 IEEE Radio Frequency Integrated Circuits Symposium 2009;7–9 June 2009.

5. A 10b/12b 40 kS/s SAR ADC With data-driven noise reduction achieving up to 10.1b ENOB at 2.2 fJ/conversion-step;Harpe;IEEE J. Solid-State Circuits,2013

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