Design and analysis of multiplier using approximate 4-2 compressor

Author:

Manikantta Reddy Karri,Vasantha M.H.,Nithin Kumar Y.B.,Dwivedi Devesh

Funder

Department of Electronics and Information Technology, Ministry of Communication & IT, Government of India

Media Lad Asia

Publisher

Elsevier BV

Subject

Electrical and Electronic Engineering

Reference25 articles.

1. New metrics for the reliability of approximate and probabilistic adders;Liang;IEEE Trans Comput,2013

2. Low power CMOS pass logic 4–2 compressor for high-speed multiplication;Radhakrishnan;Proc of the 43rd IEEE Midwest Sympos Circuits and Systems,2000

3. Low-power digital signal processing using approximate adders;Gupta;IEEE Trans Comput-Aid Des Integr Circ Syst,2013

4. Memristor augmented approximate adders and subtractors for image processing applications: an approach;Muthulakshmi;AEU – Int J Electron Commun,2018

5. A low-power, high-performance approximate multiplier with configurable partial error recovery;Liu;Des Automat Test in Europe Conf Exhib (DATE), Dresden,2014

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