FPGA implementation of self organizing map with digital phase locked loops
Author:
Publisher
Elsevier BV
Subject
Artificial Intelligence,Cognitive Neuroscience
Reference10 articles.
1. IP core implementation of a self-organizing neural network;Hendry;IEEE Transactions on Neural Networks,2003
2. A new digital pulse-mode neuron with adjustable activation function;Hikawa;IEEE Transactions on Neural Networks,2003
3. Hikawa, H. (2005). A new pulse mode self organizing map hardware with digital phase locked loops. Conference CDROM Proceedings of the IJCNN2005.
4. All digital phase-locked loop with a wide locking range;Hikawa,1986
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