1. V. Aparin, G. Brown, L.E. Larson, Linearization of CMOS LNAs via optimum gate biasing, in: Proceedings of the IEEE International Symposium on Circuits Systems, Vancouver, BC, Canada, vol. 4, May 2004, pp. 748–751.
2. Y. Ding R. Harjani, A +18dBm IIP3 LNA in 0.35µm CMOS, in: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers, Feb. 2003, pp. 162–163.
3. Y.S. Youn, J.H. Chang, K.J. Koh, Y.J. Lee, H.K. Yu, A 2GHz 16dBm IIP3 Low Noise Amplifier in 0.25µm CMOS Technology, in: Proceedings of the IEEE International Solid-State Circuits Conference (ISSCC), vol. 1, Feb. 2003, pp. 452–453.
4. A 5.5-mW +9.4-dBm IIP3 1.8-dB NF CMOS LNA employing multiple gated transistors with capacitance desensitization;Jin;IEEE Trans. Microw. Theory Tech.,2010
5. A common-gate amplifier with transconductance nonlinearity cancellation and its high analysis using the volterra series;Kim;IEEE Trans. Microw. Theory Tech.,2009