Measurements of the effect of jitter on the performance of clock retiming circuits for on-chip interconnects

Author:

Kadayinti NaveenORCID,Shojaei Baghini Maryam,Sharma Dinesh K.

Funder

Tata Consultancy Services

Publisher

Elsevier BV

Subject

General Engineering

Reference11 articles.

1. Current-mode transceiver for silicon interposer channel;Lee;IEEE J. Solid State Circ.,2014

2. Power efficient gigabit communication over capacitively driven RC-limited on-chip interconnects;Mensink;IEEE J. Solid State Circ.,2010

3. Flip-flop and repeater insertion for early interconnect planning;Lu,2002

4. A 9.6-Gb/s 1.22-mW/Gb/s data-jitter mixing forwarded-clock receiver in 65-nm CMOS;Chung;IEEE Trans. Very Large Scale Integr. Syst.,2015

5. Settling time of mesochronous clock re-timing circuits in the presence of timing jitter;Kadayinti,2017

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