Author:
Pable S.D.,Hasan Mohd.,Abbasi S.A.,Alamoud A.R.M.
Funder
Department of Science and Technology, Ministry of Science and Technology, India
Reference37 articles.
1. T. Kuroda, Optimization and control of VDD and VTH for low power, high speed CMOS design, in: Proceedings of ICCAD, 2002, pp. 28–34.
2. W.H., Chen Wang, W. Kudva, R. Gristede, G. Kosonocky, S. Joshi, Mixed multi-threshold differential cascode voltage switch circuit style and strategies for low power VLSI, International Symposium on Low Power Electronics and Design, 2001, pp. 263–266.
3. Leakage minimization of SRAM cells in a dual-Vt and dual-Tox technology;Amelifard;IEEE Trans. Very Large Scale Integr. (VLSI) Syst.,2008
4. J. Cong, An interconnect-centric design flow for nanometer technologies, International symposium on VLSI Technology, System, and Application, 1999, pp. 54–57.
5. Low-power design techniques for scaled technologies;Paul;INTEGR. VLSI J.,2009
Cited by
8 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献