1. A 10-bit 300 MS/s pipelined ADC with digital calibration and digital bias generation;Fang;IEEE J. Solid State Circuits,2013
2. A 12b ENOB, 2.5MHz-BW, 4.8mW VCO-based 0-1 MASH ADC with direct digital background calibration;Ragab;IEEE J. Solid State Circuits,2016
3. Optimizing the stage resolution in pipelined SAR ADCs for high-speed high-resolution application;Sun;IEEE Trans. Circuits Syst.,2014
4. A 0.02mm265nm CMOS 30MHz BW all-digital differential VCO-based ADC with64dB SNDR;Daniels;IEEE VLSI Dig. Tech. Pap.,2010
5. An uncalibrated 2MHz, 6mW, 63.5dB SNDR discrete-time input VCO-based ΔΣ ADC;Hamilton;IEEE Cust. Integr. Circuits Conf.,2012