Author:
Liu Xiaonian,Xu Yiran,Fan Xiangquan,Liao Mengxing,Li Pingliang,Zou Shichang
Reference13 articles.
1. A novel symmetrical split-gate structure for 2-bit per cell flash memory;Fang;Chin. J. Semicond.,2014
2. A Highly reliable 2-bits/cell split-gate flash memory Cell with A new program-disturbs immune array configuration;Fang;IEEE Trans. Electron Dev.,2014
3. SPICE modeling of 55nm embedded SupperFlash technology 2T memory cells;Martinie;Microelectron. Test Struct. (ICMTS),2015
4. A 1.35-V 16Mb twin-bit-cell Virtual-ground-architecture embedded flash memory with a sensing Current protection technique;Zhang;IEEE Trans. Circ. Syst. I,2014
5. M.O. Shea, A. Concannon, K.G. McCarthy, B. Lane, Mathewson, M. Slotboom. Macro Model for EEPROM Cells, Solid-State Device Research Conference, 2000, pp. 352–355.