Line-impedance matching and signal conditioning capabilities for high-speed feed-forward voltage-mode transmit drivers

Author:

Abugharbieh Khaldoon,Balabanyan Abraham,Durgaryan Armen,Melikyan Vazgen

Publisher

Elsevier BV

Subject

General Engineering

Reference23 articles.

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2. JEDEC Standard, Low Power Double Data Rate 3 (LPDDR3), JEDEC Solid State Technology Association, 2011, pp. 138.

3. W. Mo et al., A 20Gbps on-chip transceiver with equalization technique for global signal transmission, in: Proceedings of the IEEE International Conference Electron Device and Solid State Circuit, Bangkok, Thailand, 2012, pp.1–4.

4. A 10-Gb/s 5-Tap DFE/4-Tap FFE transceiver in 90-nm CMOS technology;Bulzacchelli;IEEE J. Solid-State Circuits,2006

5. C. Choi et al., A low power 2.4-GHz CMOS direct-conversion transmitter for IEEE 802.15.4, in: IEEE International Wireless Symposium, Xi’an, China, 2014, pp.1–4.

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