Delay models and design guidelines for MCML gates with resistor or PMOS load

Author:

Centurelli Francesco,Scotti Giuseppe,Trifiletti Alessandro,Palumbo Gaetano

Publisher

Elsevier BV

Subject

General Engineering

Reference21 articles.

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5. 0.18-μm CMOS 10-Gb/s multiplexer/demultiplexer ICs using current mode logic with tolerance to threshold voltage fluctuation;Tanabe;IEEE J. Solid State Circ.,2001

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