Fine grain thermal modeling and experimental validation of 3D-ICs

Author:

Oprins H.,Srinivasan A.,Cupak M.,Cherman V.,Torregiani C.,Stucchi M.,Van der Plas G.,Marchal P.,Vandevelde B.,Cheng E.

Publisher

Elsevier BV

Subject

General Engineering

Reference14 articles.

1. The International Technology Roadmap for Semiconductors (ITRS), 2008 edition, URL: 〈http://www.itrs.net/Links/2008ITRS/Home2008.htm〉.

2. E. Beyne, The rise of the 3rd dimension for system integration, in: Proceedings of the IEEE International Interconnect Technology Conference, 2006, pp. 1–5.

3. M. Rencz, Thermal issues in stacked die packages, 21st IEEE Semi-therm Symposium, March 2005, pp. 307–312.

4. FireBolt (nanoscale full-chip thermal simulator), Gradient Design Automation, Inc., 〈http://www.gradient-da.com/〉.

5. M. Turowski,, S. Dooley, A. Raman, M. Casto, Multiscale 3D thermal analysis of analog ICs: from full-chip to device level, in: Proceedings of the 14th International Workshop on Thermal Inveatigation of ICs and Systems, 2008, pp. 64–69.

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2. Fighting Dark Silicon: Toward Realizing Efficient Thermal-Aware 3-D Stacked Multiprocessors;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2017-04

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