1. International technology roadmap for semiconductors, www.itrs.org, 2009.
2. Double pattern EDA solutions for 32nm HP and beyond;Bailey,2007
3. Application challenges with double patterning technology (DPT) beyond 45nm;Park,2006
4. Sub-40-nm half-pitch double patterning with resist freezing process;Hori,2008
5. Advanced processes for 193-nm immersion lithography;Wei,2009