Analysis and Optimization design of the column bus parasitic effects on large-array CMOS image sensor

Author:

Gao Jing,Zhang Dezhi,Nie Kaiming,Xu Jiangtao

Funder

National Natural Science Foundation of China

Tianjin Research Program of Application Foundation and Advanced Technology

Publisher

Elsevier BV

Subject

General Engineering

Reference17 articles.

1. Design of a variable resolution CMOS image sensor for a smart security system;Cho,2016

2. A 1/2.8-inch 24Mpixel CMOS image sensor with 0.9μm unit pixels separated by full-depth deep-trench isolation;Kim,2018

3. A high speed high resolution readout with 14-bits area efficient SAR-ADC adapted for new generations of CMOS image sensors;Ben Aziza,2015

4. 6.2 133Mpixel 60fps CMOS image sensor with 32-column shared high-speed column-parallel SAR ADCs;Funatsu,2015

5. Development of a 55μm pitch 8 inch CMOS image sensor for the high resolution NDT application;Kim;J. Instrum.,2016

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