1. International Technology Roadmap for Semiconductors. 2008 Update. 〈http://public.itrs.net〉.
2. Wire sizing alternative—an uniform dual-rail routing architecture;Chen;Proceedings of DATE,2008
3. A generic standard cell design methodology for differential circuit styles;Badel;Proceedings of DATE,2008
4. J. Alfredsson, B. Oelmann, Trading speed and power for reduced substrate noise from digital CMOS circuits, in: Proceedings of the IEEE International Conference on Signals and Electronic Systems, 2004.