Soft error modeling and remediation techniques in ASIC designs-Reference-Cited by-同舟云学术

Soft error modeling and remediation techniques in ASIC designs

Published:2010-08 Issue:8 Volume:41 Page:506-522
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Asadi Hossein,Tahoori Mehdi B.

Publisher

Elsevier BV

Subject

General Engineering

Reference58 articles.

1. Chip-level soft error estimation method;Nguyen;IEEE Transactions on Device and Materials Reliability,2005

2. Single event upset at ground level;Normand;IEEE Transactions on Nuclear Science,1996

3. Radiation-induced soft errors in advanced semiconductor technologies;Baumann;IEEE Transactions on Device and Materials Reliability,2005

4. S. Mitra, W. Bartlett, P. Sanda, Workshop recap, in: Proceedings of the 2nd Workshop on Silicon Errors in Logic—System Effects (SELSE), April 2006.

5. Fujitsu Corporation, in: International Solid-State Circuits Conference (ISSC), 2003.

Cited by 26 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Cross-Section Estimation for Assessment of Circuit Susceptibility to Radiation;2024 IEEE 25th Latin American Test Symposium (LATS);2024-04-09

2. Evaluating Soft Error Reliability of Combinational Circuits Using a Monte Carlo Based Method;2022 IEEE 23rd Latin American Test Symposium (LATS);2022-09-05

3. An Accurate Estimation Algorithm for Failure Probability of Logic Circuits Using Correlation Separation;Journal of Electronic Testing;2022-04

4. Soft Error Reliability Evaluation of Nanoscale Logic Circuits in the Presence of Multiple Transient Faults;Journal of Electronic Testing;2020-08

5. Analysis of the Critical Bits of a RISC-V Processor Implemented in an SRAM-Based FPGA for Space Applications;Electronics;2020-01-17