Thermal management challenges and mitigation techniques for transistor-level 3-D integration-Reference-Cited by-同舟云学术

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Thermal management challenges and mitigation techniques for transistor-level 3-D integration

Published:2019-09 Issue: Volume:91 Page:61-69
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Iqbal Md Arif^ORCID,Macha Naveen Kumar,Danesh Wafi,Hossain Sehtab,Rahman Mostafizur

Funder

National Science Foundation

Publisher

Elsevier BV

Subject

General Engineering

Reference83 articles.

1. Ultra high density logic designs using transistor-level monolithic 3D integration;Lee,2012

2. New 3-D CMOS fabric with stacked horizontal nanowires;Macha;IEEE Trans. Comput. Des. Integr. Circ. Syst.,2018

3. A review of 3-D packaging technology;Al-Sarawi;IEEE Trans. Compon. Packag. Manuf. Technol. Part B,1998

4. Liquid cooling for 3D-ICs;Shi,2011

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1. Interference Lithography‐Based Fabrication of 3D Metallic Mesostructures on Reflective Substrates using Electrodeposition‐Compatible Anti‐Reflection Coatings for Power Electronics Cooling;Advanced Electronic Materials;2024-04-27

2. 3D printable CNTs and BN hybridized PEEK composites for thermal management applications;Journal of Materials Science;2023-10

3. Thermal Evaluation for Monolithic 3D Integrated Circuits Based on Gate-all-Around Transistors;2023 International Symposium of Electronics Design Automation (ISEDA);2023-05-08

4. Fully analytical compact model for the Q–V and C–V characteristics of cylindrical junctionless nanowire FETs;Microelectronics Journal;2022-01

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