Efficient design approaches to CMOS full adder circuits

Author:

Yan AibinORCID,Bao HanORCID,Jiang Wangjin,Cui Jie,Huang Zhengfeng,Wen Xiaoqing

Funder

National Natural Science Foundation of China

Publisher

Elsevier BV

Reference34 articles.

1. 1-bit full adder design using next generation semiconductor devices and performance benchmarking at low supply voltages;Lakshmanachari;International Journal of System Assurance Engineering and Management,2024

2. Chapter "Design, Verification, Test and in Field Implications of Approximate Digital Integrated Circuits" of the Book "Approximate Computing Techniques: from Component-To Application-Level;Bosio,2022

3. Transistor downscaling toward ultra-low-power, sub-100 mum2 and sub-Hz oscillators;Barbruni,2021

4. Energy-efficient exact and approximate CNTFET-based Ternary full adders;Malik;Circ. Syst. Signal Process.,2024

5. Design of a high performance CNTFET-based full adder cell applicable in: carry ripple, carry select and carry skip adders;Tari;Microelectron. Eng.,2019

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