1. Design rule optimization of regular layout for leakage reduction in nanoscale design;Subramaniam;ASPDAC,2008
2. Modeling and analysis of line-edge roughness effect for post-lithography circuit simulation;Singhal;DAC,2007
3. Study of proximity lithography simulations using measurements of dissolution rate and calculation of the light intensity distributions in the photo resist;Sensu;SPIE,2004
4. Extending aggressive low-k1 design rule requirements for 90 and 65nm nodes via simultaneous optimization of numerical aperture, illumination and optical proximity correction;Roy;SPIE,2005
5. RADAR: RET-aware detailed routing using fast lithography simulations;Mitra;IEEE/ACM DAC,2005