A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18µm CMOS

Author:

Shen Yi,Liu Shubin,Zhu Zhangming

Funder

National Natural Science Foundation of China

Zhejiang Provincial Natural Science Foundation

Publisher

Elsevier BV

Subject

General Engineering

Reference19 articles.

1. A 10-bit 300-MS/s pipelined ADC with digital calibration and digital bias generation;Fang;IEEE J. Solid-State Circuits,2013

2. A 24-µW 11-bit 1-MS/s SAR ADC with a bidirectional single-side switching technique;Chen;IEEE Eur. Solid State Circuits Conf.,2014

3. A 10.5-b ENOB 645 nW 100kS/s SAR ADC with statistical estimation based noise reduction;Chen;IEEE Cust. Integr. Circuit Conf.,2015

4. A SAR-assisted two-stage pipeline ADC;Lee;IEEE J. Solid-State Circuits,2011

5. A 12-bit 210-MS/s 2-times interleaved pipelined-SAR ADC with a passive residue transfer technique;Lin;IEEE Trans. Circuits Syst. I,2016

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1. Design of a 10 Bit Low Power Split Capacitor Array SAR ADC;2021 IEEE International Conference on Signal Processing, Information, Communication & Systems (SPICSCON);2021-12-03

2. A 1 GS/s 10bit SAR ADC with background calibration in 28 nm CMOS;Microelectronics Journal;2021-08

3. Review—Power Approaches for Biosensors based Bio-Medical Devices;ECS Journal of Solid State Science and Technology;2020-12-01

4. A 12-bit 40-MS/s SAR ADC With a Fast-Binary-Window DAC Switching Scheme;IEEE Transactions on Very Large Scale Integration (VLSI) Systems;2018-10

5. A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS;Integration;2018-06

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