Author:
Marcon César,Webber Thais,Susin Altamiro Amadeu
Reference50 articles.
1. On the design space exploration through theu Hellfire framework;Aguiar;J. Syst. Archit.,2014
2. A generic FPGA prototype for on-chip systems with network-on-chip communication infrastructure;Arjomand;Comput. Electr. Eng.,2014
3. NoC synthesis flow for customized domain specific multiprocessor systems-on-chip;Bertozzi;IEEE Trans. Parallel Distrib. Syst.,2005
4. T. Bjerregaard, M. Stensgaard, and J. Sparsø, A scalable, timing-safe, network-on-chip architecture with an integrated clock distribution method, in: Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE’07), 2007, pp. 48–653. 〈http://dx.doi.org/10.1109/DATE.2007.364667〉.
5. Non-stationary traffic analysis and its implications on multicore platform design;Bogdan;IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.,2011
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