Impact of NBTI on performance of domino logic circuits in nano-scale CMOS

Author:

Houshmand Kaffashian M.,Lotfi R.,Mafinezhad K.,Mahmoodi H.

Publisher

Elsevier BV

Subject

General Engineering

Reference33 articles.

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3. V. De, S. Borkar, Technology and design challenges for low power and high performance [microprocessors], in: Proceedings of the International Symposium on Low Power Electronics and Design, 1999, pp. 163–168.

4. J.R.G. David, N. Bhat, A low power, process invariant keeper for high speed dynamic logic circuits, in: Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), 2008, pp. 1668–1671.

5. Process variation aware transistor sizing for load balance of multiple paths in dynamic CMOS for timing optimization;Yelamarthi;J. Comput. (JCP),2008

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2. A Design of a Non-Volatile PMC-Based (Programmable Metallization Cell) Register File;Proceedings of the 26th edition on Great Lakes Symposium on VLSI;2016-05-18

3. NBTI and Its Effect on SRAM;Robust SRAM Designs and Analysis;2012-04-09

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