Efficient ternary comparator on CMOS technology

Author:

Saha AlokeORCID,Singh Narendra Deo,Pal DipankarORCID

Publisher

Elsevier BV

Subject

General Engineering

Reference33 articles.

1. A digital comparator for use with computer display;Farmer,1969

2. A novel very low-complexity multi-valued logic comparator in nanoelectronics;Hosseini;Circ. Syst. Signal Process.,2019

3. A low-power and high-speed parallel binary comparator based on inter-stage modified binary tree structure and power-delay improved cell elements;Rahimi;Microelectronics Journal, Elsevier,2019

4. “Efficient design of magnitude and 2’s complement comparators;Ntouskas;Integrat. VLSI J.,2020

5. Scalable digital CMOS comparator using a parallel prefix tree;Abdel-hafeez;IEEE Transactions on VLSI Systems,2012

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