A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock-Reference-Cited by-同舟云学术

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A novel approach for the design of low-power pipelined synchronous systems operating in double–edge of the clock

Published:2021-01 Issue: Volume:107 Page:104947
ISSN:0026-2692
Container-title:Microelectronics Journal
language:en
Short-container-title:Microelectronics Journal

Author:

Verducci Sir Orlando^ORCID,Oliveira Duarte L.,Batista Gracieth C.,Curtinhas Tiago S.

Publisher

Elsevier BV

Subject

General Engineering

Reference38 articles.

1. Low-power state assignment techniques for finite state machines;Baccheletta,2000

2. Automatic synthesis of low-power gated-clock finite-state machines;Benini;IEEE Trans. CAD Integr. Circ. Syst.,1996

3. Car: on the highway towards de-synchronization;Bertrand,2017

4. Towards a complete methodology for synthesizing bundled-data asynchronous circuits on fpgas;Bhardwaj,2019

5. An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop;Bonetti,2015

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Synthesis of Synchronous Finite State Machines Operating on Both-Levels of the Clock Using Transparent Latches;2022 IEEE Sixth Ecuador Technical Chapters Meeting (ETCM);2022-10-11

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